The invention relates to multiple core processing, in particular to the processing of atomic memory operations.
Atomic memory operations are operations performed on a memory location such that only one operation at a time on this particular memory location can be performed at a time. In multiple core processors such atomic memory operations are typically performed on a cache line of memory. This may represent a bottle neck, because a cache line transfer across processor cores implies a one-to-many communication across cores. This is because a core requesting a cache line does not know which other core currently holds the cache line.